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CY62146V MoBL(R)
4M (256K x 16) Static RAM
Features
* * * * * * * Wide voltage range: 2.7V-3.6V Ultra-low active, standby power Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Package available in a standard 44-Pin TSOP Type II (forward pinout) package deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.
Functional Description[1]
The CY62146V is a high-performance CMOS static RAM organized as 256K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life(R) (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
256K x 16 RAM Array 2048 x 2048
SENSE AMPS
I/O0 - I/O7 I/O8 - I/O15
COLUMN DECODER BHE WE CE OE BLE
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05159 Rev. *A
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3901 North First Street
A14 A15 A16 A17
A11
A12
A13
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San Jose
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CA 95134 * 408-943-2600 Revised August 27, 2002
CY62146V MoBL(R)
Pin Configurations
TSOP II (Forward) Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A17
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................-0.5V to VCC + 0.5V DC Input Voltage[2] ................................-0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 2.7V to 3.6V
Product Portfolio
Power Dissipation VCC Range (V) Product CY62146VLL VCC(min.) VCC(typ.)[3] VCC(max.) 2.7 3.0 3.6 Speed (ns) 70 Operating ICC, (mA) Typ.[3] 7 Maximum 15 2 Standby ISB2, (A) Typ.[3] Maximum 20
Notes: 2. VIL(min.) = -2.0V for pulse durations less than 20 ns. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
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CY62146V MoBL(R)
Electrical Characteristics Over the Operating Range
CY62146V-70 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled IOUT = 0 mA, f = fMAX = 1/tRC, CMOS Levels VCC = 3.6V Test Conditions IOH = -1.0 mA IOL = 2.1 mA VCC = 2.7V VCC = 2.7V VCC = 3.6V VCC = 2.7V 2.2 -0.5 -1 -1 +1 +1 7 Min. 2.4 0.4 VCC + 0.5V 0.8 +1 +1 15 Typ.[3] Max. Unit V V V V A A mA
IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 Automatic CE Power-down Current-- CMOS Inputs Automatic CE Power-down Current-- CMOS Inputs CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = fMAX CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 VCC = 3.6V
1 2
2 20
mA A
ISB2
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC= VCC(typ.) Max. 6 8 Unit pF pF
Thermal Resistance
Parameter JA JC Description Thermal Resistance (Junction to Ambient)[4] Thermal Resistance (Junction to Case)[4] Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board BGA 55 16 TSOPII 60 22 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 R1 VCC Typ 10% GND Rise Time: 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time: 1 V/ns
(a)
(b)
THEVENIN EQUIVALENT RTH OUTPUT VTH
(c)
Equivalent to:
Note: 4. Tested initially and after any design or process changes that may affect these parameters.
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CY62146V MoBL(R)
Parameter R1 R2 RTH VTH 3.0V 1105 1550 645 1.75 Unit Ohms Ohms Ohms V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[4] tR[5] Description VCC for Data Retention) Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC= 1.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V; No input may exceed VCC + 0.3V 0 70 Conditions Min. Typ.[3] Max. 1.0 1 3.6 10 Unit V A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC
VCC(min.)
tCDR
VDR > 1.0 V
VCC(min.)
tR
CE
Switching Characteristics Over the Operating Range
Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC Cycle[9, 10] Write Cycle Time Read Cycle Time Address to Data Valid
[6]
70 ns Description Min. 70 70 10 70 25 5 20 10 20 0 70 35 5 20 70 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[7, 8] OE HIGH to High-Z CE HIGH to
[8]
CE LOW to Low-Z[7] High-Z[7, 8] CE LOW to Power-up CE HIGH to Power-down BHE / BLE LOW to Data Valid BHE / BLE LOW to Low-Z BHE / BLE HIGH to High-Z
Notes: 5. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 s or stable VCC(min.) >10 s. 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY62146V MoBL(R)
Switching Characteristics Over the Operating Range (continued)[6]
70 ns Parameter tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BHE / BLE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z
[7, 8]
Description
Min. 60 60 0 0 40 60 30 0
Max.
Unit ns ns ns ns ns ns ns ns
25 10
ns ns
WE HIGH to Low-Z[7]
Switching Waveforms
Read Cycle No. 1 [11, 12]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 [12, 13]
tRC tPD tHZCE
CE tACE OE tDOE BHE/BLE tLZOE
tHZOE
tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB ICC DATA VALID HIGH IMPEDANCE
Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW.
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CY62146V MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
[9, 14, 15]
tWC ADDRESS
CE tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O
NOTE 16
tHD
DATA VALID IN tHZOE
Write Cycle No. 2 (CE Controlled)
[9, 14, 15]
tWC ADDRESS CE tSA tAW tHA tSCE
BHE/BLE
tBW
WE
tPWE tSD tHD
DATA I/O
DATAIN VALID
Notes: 14. Data I/O is high-impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 16. During this period, the I/Os are in output state and input signals should not be applied.
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CY62146V MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[10, 15]
tWC ADDRESS
CE tAW tBW tSA tHA
BHE/BLE WE
tSD DATA I/O
NOTE 16
tHD
DATA VALID IN tHZWE
[16]
tLZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
tWC ADDRESS
CE tAW tBW tSA WE tSD DATA I/O
NOTE 16
tHA
BHE/BLE
tHD
DATAIN VALID tHZWE tLZWE
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CY62146V MoBL(R)
Typical DC and AC Characteristics
Normalized Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage 45 MoBL 40 35 ISB (A) 30 20 15 10 5 3.2 SUPPLY VOLTAGE (V) 3.7 2.7
1.4 1.2
MoBL 1.0 ICC 0.8 0.6 0.4 0.2 0.0 2.7
2.8
SUPPLY VOLTAGE (V)
3.7
Access Time vs. Supply Voltage 80 70 60 50 TAA (ns) 40 30 20 10 2.7 2.8 SUPPLY VOLTAGE (V) 3.7 MoBL
Truth Table
CE H L L L L L L L L L WE X H H H H H L L L L OE X L L L L H X X X X BHE X L H L H X L H L H BLE X L L H H X L L H H Inputs/Outputs High-Z Data Out (I/O0-I/O15) Data Out (I/O0-I/O7); I/O8-I/O15 in High-Z Data Out (I/O8-I/O15); I/O0-I/O7 in High-Z High-Z High-Z Data In (I/O0-I/O15) Data In (I/O0-I/O7); I/O8-I/O15 in High-Z Data In (I/O8-I/O15); I/O0-I/O7 in High-Z High-Z Read Read Read Output Disabled Output Disabled Write Write Write Output Disabled Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
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CY62146V MoBL(R)
Ordering Information
Speed (ns) 70 Ordering Code CY62146VLL-70ZI Package Name Z44 44-pin TSOP II Package Type Operating Range Industrial
Package Diagram
44-Pin TSOP II Z44
51-85087-A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62146V MoBL(R)
Document Title: CY62146V MoBL(R) 4M (256K x 16) Static RAM Document Number: 38-05159 REV. ** *A ECN NO. 109963 116594 Issue Date 10/02/01 09/04/02 Orig. of Change SZV GBI Description of Change Change from Spec number: 38-00647 to 38-05159 Added footnote 1. Deleted fBGA package; replacement fBGA package is available in CY62146CV30.
Document #: 38-05159 Rev. *A
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